The present invention relates to a fabricating a semiconductor package, and more particularly, to joining an integrated circuit chip to an electrical substrate by localized heating of one or more solder bumps.
An integrated circuit chip (hereinafter “chip”) may be joined to an electrical substrate (hereinafter “substrate”) using a plurality of solder connections to form a semiconductor package. The chip may generally be silicon and the substrate may be a composite substrate, a laminate substrate, or an organic laminate substrate. The solder connection may generally be formed from a lead-free tin based solder alloy.
An example of the solder connection includes controlled collapse chip connection (also known as C4 or flip-chip connection). Generally, solder connections may include an array of small solder balls on the surface of the chip before the chip is joined to the substrate. More specifically, each individual solder connection may include a bonding pad on the chip, a solder bump, and a corresponding bonding pad on the substrate. A typical joining sequence may begin with depositing or applying a plurality of solder bumps on a plurality of bonding pads on the chip. The plurality of solder bumps are then heated to a temperature sufficient to cause them to reflow. Next, the chip, including the plurality of solder bumps, is aligned to and placed on a chip site on the substrate. In doing so, the plurality of solder bumps contact a plurality of corresponding bonding pads on the substrate. The plurality of solder bumps are again heated to a temperature sufficient to cause them to reflow. The final solder connections may electrically connect and physically join the chip to the substrate to create a semiconductor package.
As presently practiced, techniques used to form the solder connection and join the chip to the substrate may subject the components of that package to a joining temperature in excess of 240° C. for as long as a few minutes. The joining temperature should be high enough to cause the solder alloy to reflow and join the chip to the substrate, as described above. In general, the chip and the substrate may have very different coefficients of thermal expansion (CTE). When the semiconductor package is cooled from the joining temperature to room temperature, the substrate may shrink more than the chip. This mismatch between coefficients of thermal expansion may cause some of the solder connections to experience shear stress proportional to the difference in the displacements of the chip relative to the substrate. Generally, solder connections located at or near a perimeter of the package experience the most stress. The shear stresses may be large enough to deform the solder connection and sometimes even cause the solder alloy to separate from the chip. In some instances, the solder connections may remain physically connected to the chip and the shear stresses may cause a top part of the chip to crack, in turn breaking wiring layers. Sometimes cracks may extend into the chip and cause further failures and defects.